As is well known in the art, for a synchronous memory device to properly operate in synchronization with a clock signal, a default value of a mode register implemented in the synchronous memory device has to be set before the synchronous memory device enters a normal operation mode. If default value of the mode register is not set, the synchronous memory device does not operate properly.
In order to ensure the proper operation of the memory device, first, the user provides an address having mode information in the mode register after power-up and before the performance of the normal operation mode. In the mode register, generally, a row address strobe (RAS) latency, a column address strobe (CAS) latency, a burst type, a burst length, etc. are programmed. The value of the mode register can be changed after power-up. However, in general, the set value of the mode register after power-up continues to be used.
Referring to FIG. 1, a circuit diagram showing a conventional mode register is illustrated. In FIG. 1, a signal PVCCH indicates a power level. The signal PVCCH has a logic low level when the power is less than a predetermined level, and has a logic high level when the power is higher than the predetermined level. A signal nPVCCH is complementary to the signal PVCCH.
When the signal PVCCH is at a logic low level, PMOS and NMOS transistors MP1 and MN1 are turned on, setting a node Ni at a logic high level and a node N2 set at a logic low level. The logic levels at the nodes N1 and N2 are respectively held in corresponding latches 12 and 14 which are composed of two latched inverters. Therefore, a default value of a signal MDST1 is set low, and a default value of a signal MDST2 is set high. The default values of the signals MDST1 and MDST2 can be changed in accordance with the corresponding mode register address signals MRA1 and MRA2. When the signal PVCCH is set to a logic high level, the PMOS and NMOS transistors MP1 and MN1 are turned off.
Now, turning to FIG. 2, a circuit diagram showing another conventional mode register is illustrated. In FIG. 2, the constituent elements that are identical to those of FIG. 1 are labeled with the same reference numerals. The mode register 10 of FIG. 2 differs from that of FIG. 1 only in that the diode-connected NMOS and PMOS transistors MN2 and MP2 are added. The NMOS and PMOS transistors MN2 and MP2 serve as a metal option, respectively. That is, the NMOS and PMOS transistors MN2 and MP2 may be formed selectively. Therefore, the respective nodes N1 and N2 can be set low or high in accordance with whether or the transistors MN2 and MP2 are formed.
The above described conventional mode register structure, however, is often inappropriate to meet the various requirements from the user. Each synchronous semiconductor memory device that comprises a mode register set with a different default value of the mode register must be manufactured separately. As a result, the variety of mode register default configurations of the respective memory devices cause an additional process burden, respectively.